The present invention relates to an impedance adjusting circuit and a semiconductor memory device having the same, and more particularly, to an impedance adjusting circuit with a reduced area.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most semiconductor devices include a receiving circuit configured to receive external signals via input pads and an output circuit configured to provide internal signals externally via output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal has a great influence on an external noise, causing the signal reflectance to become more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power voltage, a change of an operating temperature, a change of a manufacturing process, etc. The impedance mismatch may lead to a difficulty in a high-speed transmission of data and a distortion in output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, it frequently gives rise to problems such as a setup/hold failure and an error in decision of an input level.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance adjusting circuit, which is called an impedance adjusting circuit, around an input pad inside an IC chip. In a typical impedance adjusting circuit scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel with respect to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating pull-up and pull-down codes which are varied with PVT (process, voltage and temperature) conditions. The resistance of the impedance adjusting circuit, e.g., a termination resistance at a DQ pad in a memory device, is calibrated using the codes resulting from the ZQ calibration. Here, the term of ZQ calibration is attributed to the fact that the calibration is performed using a ZQ node.
Hereinafter, how the ZQ calibration is performed in an impedance adjusting circuit will be described.
FIG. 1 is a block diagram of a calibration circuit for performing a ZQ calibration in a conventional impedance adjusting circuit.
Referring to FIG. 1, the conventional impedance adjusting circuit configured to perform ZQ calibration includes a first calibration resistor circuit 110, a second calibration resistor circuit 120 and 130, a reference voltage generator 102, first and second comparators 103 and 104, and pull-up and pull-down counters 105 and 106. The first calibration resistor circuit 110 is provided with a plurality of pull-up resistors which are turned on/off in response to a pull-up calibration code PCODE<0: N>. The second calibration resistor circuit 120 and 130 includes a pull-up calibration resistor unit 120 and a pull-down calibration resistor unit 130. Here, the pull-up calibration resistor unit 120 has the same construction as the first calibration resistor circuit 110. The pull-down calibration resistor unit 130 is provided with a plurality of pull-down resistors which are turned on/off in response to a pull-down calibration code NCODE<0: N>.
The first calibration resistor circuit 110 generates the pull-up calibration code PCODE<0: N> primarily while being calibrated with an external resistor 101 connected to a ZQ node. The second calibration resistor circuit 120 and 130 generates the pull-down calibration code NCODE<0: N> secondarily using the pull-up calibration code PCODE<0: N> which has been generated through the first calibration resistor circuit 110.
The first comparator 103 compares a ZQ node voltage at the ZQ node with a reference voltage VREF (generally, set to VDDQ/2) generated from the reference voltage generator 102, thereby generating up/down signals UP/DOWN. Herein, the ZQ node voltage is generated by coupling the first calibration resistor circuit 110 to the external resistor 101 (generally, 240 Ω) connected to a ZQ pin that is disposed outside a chip of the ZQ node.
The pull-up counter 105 receives the up/down signals UP/DOWN to generate the pull-up calibration code PCODE<0: N> as a binary code, which turns on/off the pull-up resistors connected in parallel in the first calibration resistor circuit 110, thereby calibrating total resistance of the first calibration resistor circuit 110. The calibrated resistance of the first calibration resistor circuit 110 affects the ZQ node voltage again, and the above-described calibration procedure is then repeated. That is, the first calibration resistor circuit 110 is calibrated such that the total resistance of the first calibration resistor circuit 110 is equal to the resistance of the external resistor 101, which is called a pull-up calibration.
The binary code, i.e., the pull-up calibration code PCODE<0: N>, generated during the pull-up calibration is inputted into the pull-up calibration resistor unit 120 of the second calibration resistor circuit 120 and 130, thereby determining total resistance of the pull-up calibration unit 120. Thereafter, a pull-down calibration starts to be performed in a similar manner to the pull-up calibration. Specifically, the pull-down calibration unit 130 is calibrated such that a voltage of a node A is equal to the reference voltage VREF using the second comparator 104 and the pull-down counter 106, that is, the total resistance of the pull-down calibration resistor unit 130 is equal to the total resistance of the pull-up calibration resistor unit 120, which is called the pull-down calibration.
The binary codes PCODE<0: N> and NCODE<0: N> resulting from the ZQ calibration, i.e., pull-up and pull-down calibrations, are inputted to pull-up and pull-down resistors (termination resistors) at input/output pads, which are identically configured to the pull-up and pull-down calibration resistor units in the calibration circuit of FIG. 1, thus determining resistance of the impedance adjusting circuit. In a memory device, resistances of pull-up and pull-down resistors at a DQ pad are determined.
FIG. 2 is a block diagram illustrating how termination resistance of an output driver of a semiconductor memory device is determined using the calibration codes PCODE<0: N> and NCODE<0: N> generated from the calibration circuit of FIG. 1.
Referring to FIG. 2, the output driver configured to output data in the semiconductor memory device includes first and second pre-drivers 210 and 220 located at its upper and lower parts, and pull-up and pull-down termination resistor units 230 and 240 for outputting data.
The first and second pre-drivers 210 and 220 provided in the up/down circuits control the pull-up termination resistor unit 230 and the pull-down resistor unit 240, respectively. When outputting a data having a logic high level, the pull-up termination resistor unit 230 is turned on so that a data pin DQ goes to ‘HIGH’ state. On the contrary, when outputting a data having a logic low level, the pull-down termination resistor unit 240 is turned on so that the data pin DQ goes to ‘LOW’ state. That is, the data pin DQ is pull-up or pull-down terminated to thereby output a data of a logic high level or a logic low level.
At this time, the number of resistors in the pull-up and pull-down termination resistors 230 and 240 to be turned on is determined by the pull-up and pull-down calibration codes PCODE<0: N> and NCODE<0: N>. Specifically, which resistor unit is turned on between the pull-up and pull-down termination resistor units 230 and 230 is mainly determined depending on a logic level of output data, but which resistor is turned on among the termination resistors provided in one of the termination resistor units 230 and 240 that has been selected to be turned on is determined by the pull-up calibration code PCODE<0: N> or pull-down calibration code NCODE<0: N>.
For reference, target resistances of the pull-up and pull-down resistor units 230 and 240 are not necessarily equal to resistances (240 Ω) of the first and second resistor circuits (see “110”, “120” and “130” of FIG. 1) but may have a resistance of one-half (120 Ω) or one-quarter (60 Ω) of 240 Ω, etc. In FIG. 2, reference symbols “DQP_CTRL” and “DQN_CTRL” inputted to the first and second pre-drivers 210 and 220 denote various control signals exemplarily.
FIG. 3 illustrates a procedure while the ZQ node voltage is equalized to the reference voltage through the calibration operation of FIG. 1.
In FIG. 3, there is shown bang-bang error occurring when the pull-up calibration code PCODE<0: N> is generated. The bang-bang error is a phenomenon that the ZQ node voltage keeps rising and falling at regular steps with respect to the reference voltage VREF during the calibration operation because the ZQ node voltage is not accurately equal to the reference voltage VREF.
FIG. 4 is a block diagram illustrating another conventional calibration circuit in which the comparator of FIG. 1 is improved so as to remove the bang-bang error shown in FIG. 3.
While the conventional calibration circuit of FIG. 1 employs the two comparators 103 and 104, another calibration circuit of FIG. 4 employs four comparators, i.e., first to fourth comparators 403_1, 403_2, 404_1 and 404_2, and first and second hold logics 407 and 408 located at upper and lower parts respectively.
As for a basic pull-up operation, the first comparator 403_1 compares the ZQ node voltage with a first reference voltage VREF+A, and the second comparator 403_2 compares the ZQ node voltage with a second reference voltage VREF−A. The case where outputs of the first and second comparators 403_1 and 403_2 differ from each other means that the ZQ node voltage is in the range between the first reference voltage VREF+A and the second reference voltage VREF−A. In this case, the first hold logic 407 generates a first hold signal P_HOLD to disable an operation of a first counter 405 and fixes the pull-up calibration code PCODE<0: N>. When the first hold signal P_HOLD is not activated, the counting of the first counter 405 is performed based on a first count signal P_CNT which is one of two outputs of the first and second comparators 403_1 and 403_2. Likewise, a pull-down operation is performed in the same manner as the pull-up operation.
FIG. 5 is a circuit diagram illustrating the first hold logic 407 in the calibration circuit of FIG. 4. The second hold logic 408 has substantially the same structure as that of the first hold logic 407.
Herein, reference symbols “OUT_A” and “OUT_B” denote the output signals of the two comparators 403_1 and 403_2 or 404_1 and 404_2. When the output signals OUT_A and OUT_B have different logic levels, the first hold signal P_HOLD is activated to a logic high level and thus the counting of the first and second counters 405 or 406 is performed using the first count signal P_CNT having the same logic level as the output signal OUT_A.
FIG. 6 illustrates a procedure while the ZQ node voltage is equalized to the reference voltage through the calibration operation described with reference to FIG. 4.
As shown in FIG. 6, it can be observed that the ZQ node voltage is fixed to a predetermined level once the ZQ node voltage falls within a target range.
FIG. 7 is a block diagram illustrating transmission of the calibration codes generated from a conventional calibration circuit 710 to an output driver 720.
Referring to FIG. 7, the pull-up calibration code PCODE<0: N> and the pull-down calibration code NCODE<0: N>, which are generated in the conventional calibration circuit 710, are transferred to the output driver 720 through metal lines. Here, the number of metal lines should be 2*(N+1) because a total number of the pull-up and pull-down calibration codes is 2*(N+1). Such a great number of metal lines lead to increased chip area.